1. Field of the Invention
The present invention relates to a semiconductor memory device having an EDO (Extended Data Out) function.
2. Description of the Related Art
In order to take advantage of the increasingly faster processing speeds of today's central processing units (CPUs), it is important to provide semiconductor memory devices which are designed to have faster operational speeds. The importance of matching increasingly fast CPUs with increasingly fast memory devices can be seen by the expanding demand for faster and more powerful microprocessor systems. These semiconductor memory devices frequently come equipped with an Extended Data Output function (EDO), effectively extending the time available for the device to perform data output reading operations. This ensures enhanced reading reliability despite the memory device's increased operational speed. Consequently, a demand currently exits to increase the data reading speed of EDO type semiconductor memory devices.
FIG. 1 shows the general constitution of a DRAM having an EDO function. Control signals /RAS (Row Address Strobe) and /CAS (Column Address Strobe), externally input to control the operation of the DRAM, are supplied to an address buffer 1. The control signal /RAS is input to the address buffer 1 as a signal to latch the row address, while the control signal /CAS is input to the address buffer 1 as a signal to latch the column address. The control signal /RAS is also input as an enable signal to an input/output (I/O) buffer circuit 2 and to a write clock generator 3. The control signal /CAS is likewise input to the I/O buffer circuit 2 as an I/O control signal, and to the write clock generator 3 as a signal to latch a write enable signal /WE that is also provided as input to the generator 3.
Based on the control signals /RAS and /CAS, address signals A0 to A9 input to the address buffer are latched in the address buffer 1 and output therefrom to a row decoder 4 and a column decoder 5. Based on the address signals A0-A9, the row decoder 4 and column decoder 5 select specific memory cells from among a plurality of memory cells in a memory cell array 6. In cell-data read mode, cell data read from the selected memory cells is output as output data Dout via a sense amplifier, an I/O gate 7 and the I/O buffer circuit 2. In cell-data write mode, write data Din input to the I/O buffer circuit 2 is written in the selected memory cells in the memory cell array 6 via the sense amplifier and I/O gate 7. The I/O buffer circuit 2 is controlled based on the write control signal /WE, input via the write clock generator 3 to the I/O buffer circuit 2, and on the aforementioned control signals /RAS and /CAS.
The output buffer section in the I/O buffer circuit 2 will be described below with reference to FIG. 2. In cell-data read mode, read data CB and /CB, read onto common buses from the sense amplifier and I/O gate 7, are input to transfer gates Tr1 and Tr2 each formed from a single N channel MOS transistor. The read data CB is input via the transfer gate Tr1 to a latch circuit 8a, and the read data /CB is input via the transfer gate Tr2 to a latch circuit 8b. A latch control signal LA1, output from a transfer gate controller 9, is input to the gates of the transfer gates Tr1 and Tr2. The transfer gate controller 9 functions based on the control signals /RAS and /CAS. This transfer gate controller 9 is formed from a single NOR gate 14. The NOR gate 14 outputs a high level latch control signal LA1 when the control signals /RAS and CAS both go low, and a low level latch control signal LA1 when at least one of the control signals /RAS and /CAS goes high.
The output signal of the latch circuit 8a is input to the gate of an N channel MOS transistor Tr3. The output signal of the latch circuit 8b is input to the gate of an N channel MOS transistor Tr4. The transistor Tr3 has its drain connected to a high-potential power supply Vcc and its source connected to both an output terminal T.sub.o and the drain of the transistor Tr4. The transistor Tr4 has its source connected to a low-potential power supply Vss. The transistors Tr3 and Tr4 constitute an output buffer 10. In the output buffer 10, either one of the transistors Tr3 and Tr4 is turned on, based on complementary signals sent from the latch circuits 8a and 8b. In accordance with the switching action of the transistor Tr3 or Tr4, the output data Dout is output from the output terminal T.sub.o.
Referring to FIG. 3, a description will now be given of the operation of the DRAM in page mode where data is continuously read out by sequentially changing the column address at a time that the row address remains fixed. When the level of the control signal /CAS falls low following a drop in the control signal /RAS, cell data is output as the read data CB and /CB on the common buses at a predetermined time lag, in accordance with the selected column address. Following a slight lag time t3 after the falling of the control signal /CAS, the latch control signal LA1 goes high.
The timing at which the read data CB and /CB are read onto the common buses partially overlaps the timing at which the latch control signal LA1 maintains its H level. If the transfer gates Tr1 and Tr2 are turned on when control signal LA1 is high, the read data CB and /CB will be output as output data Dout from the output terminal T.sub.o via the latch circuits 8a and 8b as well as from the output buffer 10. This output occurs approximately in synchronism with the reading of read data CB and /CB onto the common buses.
Subsequently, when the control signal /CAS changes to a high level from a low level, the latch control signal LA1 goes low with a slight delay of time t3. As a result, the transfer gates Tr1 and Tr2 are turned off, and the read data CB and /CB are latched in the latch circuits 8a and 8b. Based on the latched data, the output data Dout remains being output. Should the column address signal be altered while the latched data is output, the control signal /CAS returns to a low level again. Then, new cell data is output as the read data CB and /CB on the common buses, based on a newly selected column address. The read data CB and /CB are then latched by the latch circuits 8a and 8b and are output as output data Dout in the above-described manner. Every time the level of the control signal /CAS falls low from a high level, therefore, cell data read from the selected memory cell is output as output data Dout with a predetermined time lag from the falling of the control signal /CAS.
According to the conventional DRAM, after the control signal /CAS changes from a low to a high level, the latch control signal LA1 falls low. In response to the falling of the control signal LA1, the read data CB and /CB read onto the common buses are latched in the latch circuits 8a and 8b. It is thus necessary to keep the control signal /CAS at a L level until the cell data read from the selected memory cell is output on the common buses as the read data CB and /CB.
One way to shorten the data reading cycle in conventional DRAMs, would be to shorten the operation time t4, shown in FIG. 3, from the point when the control signal /CAS falls low to the point when the read data CB and /CB are read out on their common buses. To accomplish this, significant improvements must be made to the structure of the memory cells, the cell layout or on the load driving performance of the sense amplifier. Such improvements, however, are not easily accomplished.
An alternative method to shorten the operation time t4 would be to alter the column address signal using faster timing in response to a falling control signal /CAS. Changing the column address signal this way, however, entails longer periods of time for setting up the column address signal. This presents a conflict between the specifications of the DRAM and the DRAM's control device.